What is LVDS?
LVDS (Low Voltage Differential Signaling) is a small-amplitude differential signaling technology that uses very low-amplitude signals (250mV~450mv) to transmit data through a pair of parallel PCB traces or balanced cables.
Benefits of LVDS Technology
The transmission standard of LVDS uses a current mode to drive the output, which does not generate ringing and peak signals caused by signal switching, and has good EMI characteristics.
Low power consumption
Since the LVDS differential signaling technique reduces noise concerns, lower signal voltage amplitudes can be used. This feature is very important, it makes it possible to increase the data transfer rate and reduce power consumption. Low drive amplitude means data can be reversed faster.
High efficient transfer
Since the driver is a constant current source mode, the power consumption hardly changes with the frequency, and the power consumption of a single channel is very low. Therefore, after adopting this technology, as long as the length of a pair of parallel transmission lines is consistent enough, and a good matching termination impedance technology is provided at the receiving end to reduce the generation of reflected signals, a very high data transmission rate can be provided.
How does LVDS work?
The schematic diagram below explains how LVDS work. Its driver consists of a constant current source (usually 3.5mA) driving a pair of differential signal lines. The current and voltage amplitudes flowing through the two parallel differential signal lines are opposite, and the noise signal is coupled to the two lines at the same time. The receiver only cares about the difference between the two signals, so the noise is canceled out. Since the electromagnetic fields around the two signal lines also cancel each other out, differential signal transmission has much less electromagnetic radiation than single-line signal transmission. There is a high DC input impedance at the receiver (which draws almost no current), so almost all of the drive current will flow through the 100 ohm terminating resistor to produce about 350mV at the receiver input.
When the driving state is reversed, the direction of the current flow through the resistor is changed, thus producing an effective “0” or “1” logic state at the receiving end.
Features of LVDS
- High-speed transmission capability up to 2Gbps;
- Low voltage, low power consumption;
- LVDS adopts CMOS process;
- Low static power consumption;
- Low noise radiation;
- The use of differential transmission mode has strong anti-interference ability.
LVDS Signal Design Rules
In the process of designing lvds signals, please consider the following factors:
1. Electromagnetic interference
LVDS signal filter design is mainly for filter design such as clock signal and bus signal. The clock signal is added with an RC filter design at the sending end to reduce the external radiation interference of the clock. For differential signals, the filter design needs to add common-mode inductors at the port to filter and suppress common-mode noise.
2. Interference with fixed paths
The interference path is generally the power supply or signal line, so the LVDS circuit design only needs to add a protection design to the interface, increase the capacitance to the ground after adding magnetic beads to absorb the interface, so that the interference can be released through the fastest path.
3. Environmental interference
This interference is caused by electromagnetic radiation from external sources in the environment, and protective measures such as adding ferrite beads and capacitors are often used to reduce the effects of this interference.
To reduce crosstalk between single-ended signals and LVDS signals, follow:
- Single-ended signals at least 12 mm away from LVDS signals on the same PCB layer;
- The distance between the differential lines should not exceed twice the width of the signal lines, and the thickness of the circuit board should be greater than the distance between the signal lines;
- The distance between two adjacent differential pairs should be greater than or equal to 2 times the distance between independent signal lines.
4. Impedance matching
When designing impedance matching for LVDS signals, the following should be followed:
- The PCB should be at least 4 layers, and LVDS signals and TTL/CMOS signals need to be isolated with power planes or ground planes; LVDS drivers and receivers should be placed as close to the connector as possible;
- Place a 4.7μF or 10μF capacitor close to the Vcc pin of the driver or receiver, and consider the matching between the operating frequency of the signal and the optimal operating frequency of the capacitor;
- Place at least one 0.1µF and one 0.001µF capacitor close to a driver or receiver Vcc pin;
- Power and ground traces should be as wide as possible to reduce power return impedance.